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 PLL502-39U
750kHz - 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC's
FEATURES
* * * * * * * * * Selectable 750kHz to 800MHz range. Low phase noise output (@ 10kHz frequency offset, -142dBc/Hz for 19.44MHz, -125dBc/Hz for 155.52MHz, -115dBc/Hz for 622.08MHz). 12 to 25MHz crystal input. No external load capacitor or varicap required. Inverted LVDS signal Output Enable selector. Wide pull range (+/-200 ppm) Selectable 1/16 to 32x frequency multiplier. 3.3V operation. Available in 16-Pin (TSSOP or 3x3mm QFN).
PIN CONFIGURATION (Top View)
SEL0^
10
XOUT SEL3^ SEL2^ OE
13 14 15 16
12
11
SEL1^
9
XIN
VDD
8 7 6 5
GND CLKC VDD CLKT
PLL502-39U
1 2 3 4
DESCRIPTION
VCON GND GND
The PLL502-39U (LVDS) is a high performance and low phase noise VCXO clock IC. It provides phase noise performance as low as -125dBc at 10kHz offset (at 155MHz), by multiplying the input crystal frequency up to 32x. The wide pull range (+/- 200 ppm) and very low jitter makes this ideal for a wide range of applications, including SONET/SDH and FEC. PLL502-39 accepts fundamental parallel resonant mode crystals input from 12 to 25MHz.
Note: ^ designates Internal pull-up
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL502-39U
OE
1 0 (Default) Tri-state
GND
State
Output enabled
BLOCK DIAGRAM
SEL OE VCON Oscillator XIN XOUT
Amplifier w/ integrated varicaps PLL (Phase Locked Loop)
CLKC CLKT
PLL by-pass
PLL502-39U
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 1
PLL502-39U
750kHz - 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC's
FREQUENCY SELECTION TABLE
SEL3 0 0 0 1 1 1 1 1 1 1 SEL2 0 1 1 0 0 0 1 1 1 1 SEL1 1 1 1 0 1 1 0 0 1 1 SEL0 1 0 1 1 0 1 0 1 0 1 Selected Multiplier Fin x 32 Fin / 8 Fin x 2 Fin / 2 Fin / 16 Fin x 4 Fin / 4 Fin x 8 Fin x 16 No multiplication
PIN DESCRIPTIONS
Name VCON GND CLKT VDD CLKC SEL1 SEL0 VDD XIN XOUT SEL3 SEL2 OE 3x3mm QFN Pin number 1 2,3,4,8 5 6 7 9 10 11 12 13 14 15 16 Type I P O P O I I P I I I I I Voltage Control input. Ground connection. LVDS Output +3.3V power supply. Complementary LVDS output Multiplier selector pins. These pins have an internal pull-up that will default SEL to `1' when not connected to GND. +3.3V power supply. Crystal input. See Crystal Specification on page 3. Crystal output. See Crystal Specification on page 3. Multiplier selector pins. These pins have an internal pull-up that will default SEL to `1' when not connected to GND. Output enable pin (see OE logic state table on page 1). Description
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 2
PLL502-39U
750kHz - 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC's
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model
SYMBOL
VDD VI VO TS TA TJ
MIN.
-0.5 -0.5 -65 -40
MAX.
4.6 VDD+0.5 VDD+0.5 150 85 125 260 2
UNITS
V V V C C C C kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications PARAMETERS
Crystal Resonator Frequency Crystal Loading Rating Crystal Pullability Recommended ESR
SYMBOL
FXIN CL (xtal) C0/C1 (xtal) RE
CONDITIONS
Parallel Fundamental Mode At VCON = 1.65V AT cut AT cut
MIN.
12
TYP.
9.5
MAX.
25 250 30
UNITS
MHz pF
Note: Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the crystal will be at nominal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range.
3. Voltage Control Crystal Oscillator PARAMETERS
VCXO Stabilization Time * VCXO Tuning Range CLK output pullability VCXO Tuning Characteristic Pull range linearity VCON pin input impedance VCON modulation BW
SYMBOL
TVCXOSTB
CONDITIONS
From power valid FXIN = 12 - 25MHz; XTAL C0/C1 < 250 0V VCON 3.3V VCON=1.65V, 1.65V
MIN.
TYP.
MAX.
10
UNITS
ms ppm ppm ppm/V % k kHz
500 200 150 10 2000 25
0V VCON 3.3V, -3dB
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 3
PLL502-39U
750kHz - 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC's 4. General Electrical Specifications PARAMETERS
Supply Current, Dynamic (with Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current
SYMBOL
IDD VDD @ 1.25V
CONDITIONS
Fout<24MHz 24MHzMIN.
TYP.
MAX.
25 45 80 3.63
UNITS
mA V % mA
2.97 4 50 50
55
5. Jitter Specifications PARAMETERS CONDITIONS
With capacitive decoupling between VDD and GND. Over 10,000 cycles.
FREQUENCY
19.44MHz 77.76MHz 155.52MHz 622.08MHz 19.44MHz 77.76MHz 155.52MHz 622.08MHz 155.52MHz 622.08MHz
MIN.
TYP.
2.2 4.5 4.5 5.0 17 25 27 35 2.5 2.5
MAX.
UNITS
Period jitter RMS
ps
Period jitter Peak-toPeak 1
With capacitive decoupling between VDD and GND. Over 10,000 cycles. Integrated 12 kHz to 20 MHz
ps
Integrated jitter RMS
4 4
ps
6. Phase Noise Specifications PARAMETERS
Phase Noise relative to carrier (typical)
FREQUENCY
19.44MHz 77.76MHz 155.52MHz 622.08MHz
@10Hz
-80 -72 -65 -55
@100Hz
-108 -103 -95 -85
@1kHz
-132 -122 -120 -109
@10kHz
-142 -130 -125 -115
@100kHz
-150 -125 -121 -110
UNITS
dBc/Hz
Note: Phase Noise measured at VCON = 0V
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 4
PLL502-39U
750kHz - 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC's 8. LVDS Electrical Characteristics PARAMETERS
Output Differential Voltage VDD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current
SYMBOL
VOD VOD VOH VOL VOS VOS IOXD IOSD
CONDITIONS
MIN.
247 -50
TYP.
355
MAX.
454 50
UNITS
mV mV V V V mV uA mA
RL = 100 (see figure)
1.4 0.9 1.125 0 1.1 1.2 3 1 -5.7
1.6 1.375 25 10 -8
Vout = VDD or GND VDD = 0V
9. LVDS Switching Characteristics PARAMETERS
Differential Clock Rise Time Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
tr tf
CONDITIONS C L = 10 pF (see figure)
RL = 100
MIN.
0.2 0.2
TYP.
0.7 0.7
MAX.
1.0 1.0
UNITS
ns ns
LVDS Switching Test Circuit
OUT
50
CL = 10pF
VOD
VOS
VDIFF
RL = 100
50 CL = 10pF OUT OUT
LVDS Transistion Time Waveform
OUT 0V (Differential) OUT
80% VDIFF 20% 0V
80%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 5
PLL502-39U
750kHz - 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC's PACKAGE INFORMATION 16 Pin 3x3 QFN D A A A
E
e L b
Symbol A A1 b D E e L Dimension in MM Min. Max. 0.70 0.80 0.203 REF 0.18 0.30 2.90 3.10 2.90 3.10 0.50 BSC 0.30 0.50 Dimension in inch Min. Max. 0.028 0.032 0.008 REF 0.007 0.012 0.114 0.122 0.114 0.122 0.020 BSC 0.012 0.020
ORDERING INFORMATION
For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type, Operating temperature range, shipping method PLL 5 02- 39 U X X- R
PART NUMBER
PACKAGE TYPE Q=QFN NONE= TUBE -R=TAPE AND REEL TEMPERATURE C=COMMERCIAL I=INDUSTRAL
Order Number
PLL502-39UQC PLL502-39UQC-R
Marking
P502-39UQC P502-39UQC
Package Option
16-Pin 3x3 QFN (Tube) 16-Pin 3x3 QFN (Tape and Reel)
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 6


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